(a) Field of the Invention
The present invention relates to a method and a system of data processing for designing a semiconductor device and, more particularly, to a technique for designing a semiconductor device by using CAD data and a combination of cell base blocks and gate array blocks.
(b) Description of the Related Art
Master slice technique is generally used for designing semiconductor devices such as an LSI. The master slice technique uses a semiconductor wafer called master slice, wherein a large number of basic circuit elements are arrayed in each chip without interconnections therebetween. A user can design a desired semiconductor device or customized master slice by designing specific interconnections in the master slice.
A data processing system is also known which assists the user in the circuit design for the master slice. The data processing system typically includes a computer system or CAD system wherein a control program for assisting the circuit design is installed for a computer. In this case, the master slice itself is prepared as a part of the CAD data to which other data such as for the desired interconnections are added by the user to obtain final CAD data.
In the up-to-date design technique using the master slice scheme, the simple arrangement of the basic circuit elements in the master slice as described above is replaced by a new complicated arrangement wherein a plurality of gate array blocks, a plurality of cell base blocks and a plurality of intermediate blocks are arranged based on the design data provided by the user.
The gate array block includes a plurality of transistors arranged without interconnections therebetween, to which the user adds desired interconnections to obtain desired logic circuits. On the other hand, the cell base block includes a plurality of circuit elements arranged with specific interconnections therebetween to form a logic gate or a logic circuit having a specific function. Each cell base block forms a specified-type logic circuit, and a plurality of cell base blocks having different types of logic circuits are prepared before the design of a specific semiconductor device.
The intermediate block is generally disposed at a boundary between a gate array block and a cell base block for preventing the interference therebetween.
These different types of blocks are arranged based on the design data for the desired semiconductor device while selecting the interconnections for the blocks, whereby CAD data for a customized master slice implementing the desired semiconductor device can be obtained without a complicated design process.
A process for preparing the CAD data for the customized master slice will be exemplified below.
First, data for a gate array block and a plurality of types of cell base blocks and an intermediate block are stored in a netlist, and data for the area of the chip or site are stored as an information file.
In general, the site on which blocks are to be arranged is separated into a pair of imaginary planes including a gate array plane and a cell base plane, on each of which a specific type of blocks can be arranged. By combining the pair of imaginary planes to obtain an overlapping plane at each step of the process, all the data for the site can be obtained on the overlapping plane.
Thus, the gate array plane and the cell base plane are defined for the single site in this process. The gate array plane can receive therein a gate array block, whereas the cell base plane can receive therein a cell base block and an intermediate block.
After the data as described above are prepared, the user inputs design data for a desired semiconductor device, whereby a specific cell base block or cell base blocks are disposed in a specified portion of the cell base plane based on the design data.
After the cell base blocks are disposed in the cell base plane, a plurality of gate array blocks are consecutively arranged on the gate array plane in an area other than the area wherein the cell base block is disposed as viewed on the overlapping plane. Then, intermediate blocks are consecutively disposed on the cell base plane in the areas other than the area wherein the cell base block or the gate array block is disposed as viewed on the overlapping plane. By overlapping the final gate array plane and the final cell base plane, desired master slice data can be obtained on the final overlapping plane.
In the process as described above, the cell base block is disposed in the area of the site based on the design data. That is, a plurality of logic circuits are arranged in the area desired by the user, with the other area not specified by the design data being filled with the gate array blocks without interconnections.
Then, data for interconnections are added to the gate array blocks to form logic circuits, and the data for the interconnections between the cell base blocks and the gate array blocks are added to connect the blocks together, thereby obtaining desired CAD data or customized master slice data for the semiconductor device.
In the gate array block including a plurality of transistors, the locations of the diffused regions for the well contact and the substrate contact are fixed sandwiching therebetween the transistors. In this configuration, a plurality of gate array blocks can be arranged adjacent to each other without interference therebetween. However, a plurality of cell base blocks forming different types of logic circuits have respective circuit arrangements which may interfere with the arrangement of an adjacent gate array block depending on the type of the logic circuit of the cell base block. The interference may arise between the diffused regions in the respective blocks. Thus, a manual examination is conducted as to whether or not the interference arises between a cell base block and an adjacent gate array block.
If the interference is found between a cell base block and an adjacent gate array block, the gate array block is replaced by an intermediate block.
In the above procedure, there is a problem in that the manual examination for the interference lowers the efficiency in the data processing in the CAD system. Although the examination and replacement of the block itself may be conducted by using a program for the CAD system, there arises the problem that the scale for the program increases and the large-scale program prolongs the processing time for the CAD system.
In an alternative, a functional area for preventing the interference may be provided in each cell base block or each gate array block. However, the functional area increases the occupied area for the block.
It is therefore an object of the present invention to provide a method and a system for designing a customized master slice for a semiconductor device by using a CAD data, which is capable of preventing the interference between adjacent blocks.
It is also an object of the present invention to provide a storage device for storing a program which is capable of allowing a CAD system to design a customized master slice for a semiconductor device while preventing the interference between adjacent blocks.
The present invention provides a data processing system for designing a semiconductor device based on design data, comprising:
a block data storage section for storing first data specifying a gate array block, the gate array block including a plurality of transistors disposed in a line symmetry, second data specifying a plurality of cell base blocks, each of the cell base blocks including a plurality of transistors, third data specifying an intermediate block having a unit length and fourth data specifying a dummy gate block, the dummy gate block having a configuration obtained by reversing the gate array block around a line for the line symmetry, the gate array block and the dummy gate block having a length equal to an integral multiple of the unit length, the cell base block having an integral multiple of the unit length;
a first block arrangement section for consecutively locating at least one cell base block in a first area based on the design data, a possible number of the dummy gate blocks in a second area, and a possible number of the intermediate blocks in an area other than the first and second areas;
a block removing section for removing the dummy gate blocks after the first block arrangement section arranges the intermediate blocks;
a second block arrangement section for locating a possible number of the gate array blocks in each space generated by removing the dummy gate blocks while shifting the gate array blocks by a specified amount from a corresponding one of the removed dummy gates;
a third block arrangement section locating a possible number of the intermediate blocks in an area generated by shifting the gate array blocks; and
an output section for outputting a customized master slice data based on the operation by the first through third block arrangement sections.
The present invention also provides a method of data processing system for designing location of blocks in a semiconductor device based on design data, comprising the steps of:
storing first data specifying a gate array block, the gate array block including a plurality of transistors disposed in a line symmetry, second data specifying a plurality of cell base blocks, each of the cell base blocks including a plurality of transistors, third data specifying an intermediate block having a unit length and fourth data specifying a dummy gate block, the dummy gate block having a configuration obtained by reversing the gate array block around a line for the line symmetry, the gate array block and the dummy gate block having a length equal to an integral multiple of the unit length, the cell base block having an integral multiple of the unit length;
consecutively locating at least one cell base block in a first area based on the design data, a possible number of the dummy gate blocks in a second area, and a possible number of the intermediate blocks in an area other than the first and second areas;
removing the dummy gate blocks after the first block arranges the intermediate blocks;
locating a possible number of the gate array blocks in each space generated by removing the dummy gate blocks while shifting the gate array blocks by a specified amount from a corresponding one of the removed dummy gates;
locating a possible number of the intermediate blocks in an area generated by shifting the gate array blocks; and
outputting a customized master slice data obtained by the above steps.
In accordance with the present invention, intermediate blocks disposed between the gate array block and the gate array bock prevent the interference from occurring at the boundary between the gate array block and the cell base block.
The above and other objects, features and advantages of the present invention will be more apparent from the following description, referring to the accompanying drawings.